Method for processing a monocrystalline Si-semiconductor wafer

ABSTRACT

A method for processing a monocrystalline Si-semiconductor wafer includes a tempering step at a temperature of over 550° C. A protective layer for protecting against the penetration of metal and/or rare earth metal substances into the Si-semiconductor wafer during the tempering step is applied to the back of the Si-semiconductor wafer before the tempering step.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation of copending InternationalApplication No. PCT/DE00/00938, filed Mar. 24, 2000, which designatedthe United States.

BACKGROUND OF THE INVENTION Field of the Invention

[0002] The invention relates to a method for processing amonocrystalline Si-semiconductor wafer. The monocrystallineSi-semiconductor wafer has a front side which is at least partiallyprocessed with respect to a sequence of layer deposition processes.

[0003] Conventional microelectronic memory elements (DRAMs) mostly useoxide or nitride layers which have a dielectric constant of a maximum ofabout 8 as a storage dielectric. In order to make a storage capacitorsmaller and to produce nonvolatile memories (FRAMs), “new type”capacitor materials (dielectrics or ferroelectrics) having distinctlyhigh dielectric constants are needed. For that purpose, capacitormaterials Pb(Zr,Ti)O₃ [PZT], SrBi₂Ta₂O₉ [SBT], SrTiO₃ [ST] and(Ba,Sr)TiO₃ [BST] are known from pages 51-53 of a generic publicationentitled “Neue Dielektrika für Gbit-Speicherchips” [New Dielectrics forGbit memory chips] by W. Hönlein, Phys. Bl. 55 (1999).

[0004] The use of those new type dielectrics/ferroelectrics with highepsilon presents problems for various reasons. For one thing, those newtype materials can no longer be combined with the traditional electrodematerial (poly)silicon. For that reason, inert electrode materials suchas, for example, Pt or conductive oxides (e.g. RuO₂) must be used.Furthermore, a diffusion barrier (e.g. of TiN, TaN, Ir, IrO₂ and MoSi₂)must be inserted between the electrode material and the conductiveconnecting structure (plug) to the transistor.

[0005] Finally, the production of such structures requires a position ofthe new type high-epsilon dielectrics/ferroelectrics in an oxygenatmosphere and the usually multiple tempering of the already partiallyprocessed Si-semiconductor wafer at temperatures above 550° C.

[0006] In practice, having to use those new type substances (metal andrare earth metals) for the high-epsilon dielectric/ferroelectric, theelectrodes and the barrier layer, in connection with the requirements ofhaving to use high process temperatures which favor diffusion processes,results in a considerably increased risk of contamination of theSi-semiconductor wafer during production.

[0007] U.S. Pat. No. 5,679,405 describes a method in which an Ar gasflow is conducted over the back of a semiconductor wafer which ismounted on a substrate holder in a CVD reactor in order to reduceadsorption of contamination.

[0008] U.S. Pat. No. 5,424,224 describes a method in which the back of asemiconductor wafer is protected by application of a protective SiO₂ orSi₃N₄ layer during polishing of the front and of the edge of the wafer.The protective layer is removed again after the polishing process.

[0009] Patent Abstracts of Japan Publication No. 56-83948 describes amethod for processing a semiconductor substrate in which a layercontaining contamination and being formed of a semiconductor material orits oxide is applied to the back of the semiconductor substrate. Thecontamination is distributed in the semiconductor substrate in a latertempering step.

[0010] U.S. Pat. No. 4,053,335 describes a method for processing amonocrystalline Si-semiconductor wafer in which the semiconductor waferis subjected to a temperature treatment step at a temperature of over550° C. during the processing. Before the processing, a polycrystallinesilicon layer is applied as a getter layer to the back of theSi-semiconductor wafer. A protective layer protecting against thepenetration of contamination during the temperature treatment step, forexample a silicon nitride layer, is applied to the polycrystallinesilicon layer.

[0011] Similarly, in Patent Abstracts of Japan Publication No.54-069964, silicon nitride layers are directly applied as protectivelayers to the front and back of a semiconductor substrate through theuse of a plasma CVD process. The subsequent heat treatment step takesplace at a temperature of about 500° C. and is used for reducing contactresistances of applied electrode layers.

[0012] U.S. Pat. No. 5,716,875 describes a method for producing CMOStransistors and ferroelectric capacitors on a semiconductor substrate inwhich silicon nitride layers are applied as protective layers to theside walls of the wafer and the back of the wafer substrate. Asdescribed therein, a LPCVD process can preferably be performed for thedeposition.

[0013] In U.S. Pat. No. 5,223,734, a production method for semiconductorcomponents is described in which the back of a semiconductor wafer isthinned and roughened by chemical/mechanical planarization (CMP). Inthat process, crystal dislocations are produced in the vicinity of thesurface of the back of the wafer which are used as traps for movingcontamination. That creates a getter layer through the use of whichcontamination in the semiconductor substrate can be trapped in a heattreatment step.

SUMMARY OF THE INVENTION

[0014] It is accordingly an object of the invention to provide a methodfor processing a Si-semiconductor wafer which overcomes thehereinafore-mentioned disadvantages of the heretofore-known methods ofthis general type, which enables risks of contamination of thesemiconductor wafer to be reduced during a tempering step and in whichthe Si-semiconductor wafer is at least partially processed at the frontand is protected against contamination in a subsequent tempering step.

[0015] With the foregoing and other objects in view there is provided,in accordance with the invention, a method for processing amonocrystalline Si-semiconductor wafer, which comprises subjecting theSi-semiconductor wafer to a plurality of tempering steps at atemperature of over 550° C. A protective layer is applied to the back ofthe Si-semiconductor wafer, at least once before a tempering step. Theprotective layer protects against penetration of at least one metaland/or rare earth metal substance into the Si-semiconductor wafer duringthe tempering step. The protective layer is at least partially removedfor removing a contaminated surface area between two of the temperingsteps.

[0016] Applying the protection layer to the back of the Si-semiconductorwafer in accordance with the invention prevents metal and/or rare earthmetal substances from being able to become adsorbed at the “naked” backof the semiconductor wafer before or during the tempering step, frombeing able to pass into the monocrystalline Si material by diffusion andfrom contaminating it during the tempering step. Such contamination ofthe semiconductor material is unwanted since it can lead to animpairment of the life and/or electrical characteristics of thecomponents which are produced on the front of the semiconductor wafer.

[0017] In accordance with another mode of the invention, the protectivelayer is a Si₃N₄ barrier layer. It has been found that a nitride layerforms a decidedly efficient diffusion barrier, especially compared withPt.

[0018] In accordance with a further mode of the invention, the Si₃N₄barrier layer is preferably deposited through the use of an LPCVD (LowPressure Chemical Vapor Deposition) process. This provides a very“dense” nitride with a low etching rate and good diffusion barriercharacteristics.

[0019] In accordance with an added mode of the invention, a SiO₂ bufferlayer is suitably applied to the Si-semiconductor wafer before the Si₃N₄barrier layer is deposited. This prevents excessive tensions which canimpair the homogeneity, the mechanical stability and the diffusionbarrier effect of the Si₃N₄ barrier layer, from building up between themonocrystalline silicon substrate and the Si₃N₄ barrier layer.

[0020] In accordance with an additional mode of the invention, in asecond preferred embodiment, the protective layer is a SiO₂ barrierlayer. The SiO₂ barrier layer also counteracts contamination of themonocrystalline Si-semiconductor substrate, assuming that its effect isbased on inclusion or enhancement processes of the substance orsubstances to be kept away in the layer to a greater extent than in thecase of the Si₃N₄ barrier layer.

[0021] In accordance with yet another mode of the invention, in a thirdpreferred embodiment, the protective layer is a barrier layer which isformed of a three-layer structure and is built up of a polysiliconsublayer embedded in two SiO₂ sublayers or a multilayer structure formedof alternatingly disposed SiO₂ and polysilicon sublayers.

[0022] In accordance with yet a further mode of the invention, thethickness of the protective layer can be selected as a function of thelayer material being used, the type and dose rate of the substance orsubstances and the process conditions (particularly temperature andduration of the tempering step). The protective layer preferably has athickness of greater than 30 nm, particularly greater than 100 nm.

[0023] In accordance with yet an added mode of the invention, theprotective layer is doped with a substance acting as a trapping centerfor the substance or substances to be kept away from theSi-semiconductor substrate, particular phosphorous. The doping increasesthe inclusion or adsorption capability of the protective layer withrespect to the substance or substances.

[0024] During the processing of the front of the Si-semiconductor wafer,a number of layer deposition steps are usually carried out during whichvarious such substances (metals and/or rare earth metals) are released.In accordance with yet an additional mode of the invention, theprotective layer is subjected, after a layer deposition process, to ascrubbing for removing deposited substances and/or for partiallyremoving the protective layer to remove a more contaminated surface areaafter a layer deposition process or between two tempering steps. Theresult of this mode of the invention is that the degree of occupancy orenhancement of the protective layer with contaminating substances isreduced before the next tempering step.

[0025] In accordance with a concomitant mode of the invention, the backof the Si-semiconductor wafer is deliberately damaged in an area closeto the surface before applying the protective layer. However, a “damagelayer” formed in this manner is capable of adsorbing and “demobilizing”the substances mentioned and thus of counteracting their diffusion intothe monocrystalline Si-semiconductor substrate, additionally to theprotective layer.

[0026] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0027] Although the invention is illustrated and described herein asembodied in a method for processing a monocrystalline Si-semiconductorwafer, it is nevertheless not intended to be limited to the detailsshown, since various modifications and structural changes may be madetherein without departing from the spirit of the invention and withinthe scope and range of equivalents of the claims.

[0028] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

[0029] The figure of the drawing is a fragmentary, diagrammatic,cross-sectional view of a layer sequence of a DRAM memory cellconstructed in a Si-semiconductor wafer with a switching transistor anda high-epsilon or ferroelectric stack capacitor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Referring now in detail to the single figure of the drawing,there is seen an N-channel MOS transistor built up through the use ofconventional planar methods (layer deposition, layer patterning by usinglithographic and etching techniques, layer doping) on a p-dopedSi-semiconductor substrate 1.

[0031] An n+-doped drain region 2 is separated from an n+-doped sourceregion 3 by an intermediate channel 4 of substrate material. A thin gateoxide layer 5 is located above the channel 4. A polysilicon gateelectrode 6 is applied to the gate oxide layer 5.

[0032] A cover oxide layer 7, which has a contact hole 8 formed therein,is deposited above the MOS transistor 2, 3, 4, 5, 6 described above. Thecontact hole 8 is filled with an electrical connecting structure 9(plug) formed of polysilicon.

[0033] The construction and method of production of the illustratedstructure are known. A bipolar transistor, or any other monolithicsemiconductor function element, can also be provided instead of the MOStransistor 2, 3, 4, 5, 6 shown herein.

[0034] A capacitor 10 is provided above the cover oxide layer 7. Thecapacitor 10 has a lower electrode 11, an upper electrode 12 and ahigh-epsilon dielectric/ferroelectric 13 therebetween.

[0035] The high-epsilon dielectric/ferroelectric 13, for example PZT,SBT, ST or BST, is deposited through the use of an MOD (Metal OrganicDeposition) process, an MOCVD (Metal Organic Chemical Vapor Deposition)process or a sputtering process.

[0036] After the deposition of the high-epsilon dielectric/ferroelectric13, it must be tempered (“conditioned”), if necessary several times, inan oxygen-containing atmosphere at temperatures of about 550-800° C. Inorder to avoid unwanted chemical reactions of the high-epsilondielectric/ferroelectric 13 with the electrodes 11, 12, they are made ofPt (or any other sufficiently temperature-stable and inert material).

[0037] Other deposition processes are required before and after thedeposition of the high-epsilon dielectric/ferroelectric 13 in order toproduce the electrodes 11, 12.

[0038] During the tempering step mentioned above, Bi, Ba or Sr, forexample, can diffuse through the bottom Pt electrode 11 from thehigh-epsilon dielectric/ferroelectric 13. Furthermore, Pt has a highdiffusibility in Si at temperatures above about 550° C. Therefore, acontinuous barrier layer 14 of TiN, TaN, Ir, IrO₂, MoSi₂ or any othersuitable material is provided underneath the bottom Pt electrode 11 toprotect the connecting structure 9. The barrier layer 14 is also createdby a deposition process (and, if necessary, a subsequent temperingstep), which is carried out before the deposition of the Pt electrodes11, 12 and of the high-epsilon dielectric/ferroelectric 13, according tothe illustrated layer sequence.

[0039] All “new type” substances (metals and rare earth metals) neededfor the capacitor and barrier-layer build up could also come into directcontact with the usually exposed back of the Si-semiconductor wafer inthe deposition processes mentioned above. A protective layer 15 isapplied to the back of the Si-semiconductor wafer in order to preventthose substances from adsorbing at the back of the Si-semiconductorsubstrate 1 and then diffusing into it during the subsequent temperingstep or steps.

[0040] The protective layer 15 can be produced before, during or afterthe production of the MOS transistor 2, 3, 4, 5, 6. Naturally, it mustbe applied before the deposition of at least those “new type” substanceor substances, the penetration of which into the back of theSi-semiconductor wafer is to be prevented in any case. Thus, theprotective layer 15 is usually produced before the deposition of thebarrier layer 14 or, at the latest, before the deposition of the bottomPt electrode 11.

[0041] The protective layer 15 can be formed, for example, of a Si₃N₄barrier layer with a thickness of 30 nm or more under which an oxidelayer of preferably at least 10 nm thickness is optionally placed forremoving tension in the transition area. A further possibility residesin providing a “condensed” and possibly doped SiO₂ barrier layer as theprotective layer 15. Furthermore, sandwich layers formed of a dopedpolysilicon sublayer embedded in two oxide sublayers and multiple layersformed of alternating oxide sublayers and doped polysilicon sublayerscan be used. The dopant which is used can, among other things, bephosphorus, with the dopant ion (P+) acting as a complexing agent.

[0042] It has been found in practice that, among the substancesmentioned, Pt (electrode material) has a particularly high tendency tocontamination. It was possible to reduce the contamination of themonocrystalline silicon noticeably with respect to Pt at a thickness ofthe protective layer of greater than 30 nm and to reduce it by severalorders of magnitude at a layer thickness of greater than 100 nm.

[0043] However, the protective layer 15 can always keep only a limitedquantity of contamination away in accordance with its layer thickness,the process parameters that are used (e.g. temperature and duration ofthe tempering step) and the environmental dose rate of the contaminatingsubstance or substances. Cleaning steps and/or material removal stepscan be additionally provided in order to keep down the degree ofcontamination in the Si-semiconductor substrate 1 even at small layerthicknesses or under disadvantageous process conditions (e.g. frequenttempering, long tempering durations, high tempering temperatures).

[0044] Pt or other metal precipitations on the protective layer 15 canbe detached or at least their quantity can be reduced by cleaning withaqua regia after the deposition process.

[0045] Material can be removed by an etching step in which an outer,highly contaminated sublayer of, for example, less than 10 nm of theprotective layer 15 is removed. A protective nitride layer 15 can beetched, for example, with HF/HNO₃.

[0046] Both processes (cleaning and material removal) can be carried outboth in combination and repeatedly. If a number of tempering steps areprovided, a repeated removal of material, carried out between theindividual tempering steps, can also be useful for reducing the degreeof contamination.

[0047] The protective layer 15 can also be removed in a progressive andgraduated manner in accordance with the number of process steps of thestructures to be applied to the front of the Si-semiconductor substrate1. This partial and thus repeated removal of the protective layer 15contributes to lower the contamination of the back of the wafer to anattainable extent. In particular, this procedure has the advantage ofremoving the top and in each case most-contaminated layer of theprotective layer 15 relatively quickly and thus the probability offurther penetration of the contamination is distinctly reduced. Theprotective layer 15 should be applied with sufficient thickness forprogressive removal.

[0048] When using a protective layer 15 formed of a nitride barrierlayer and an oxide buffer layer, and the cleaning and material removalsteps mentioned, it was possible to verify after these layers had beenremoved through the use of TRXRF (Total Reflection X-ray Fluorescence)that the degree of Pt contamination of the Si-semiconductor substrate 1was less than 10¹¹ atoms/cm² with a wafer thickness of 1 mm.

I claim:
 1. A method for processing a monocrystalline Si-semiconductorwafer, which comprises: subjecting the Si-semiconductor wafer to aplurality of tempering steps at a temperature of over 550° C.; applyinga protective layer to the back of the Si-semiconductor wafer, at leastonce before one of the tempering steps, the protective layer protectingagainst penetration of at least one substance selected from the groupconsisting of metal substances and rare earth metal substances into theSi-semiconductor wafer during the one tempering step; and at leastpartially removing the protective layer for removing a contaminatedsurface area between two of the tempering steps.
 2. The method accordingto claim 1, which further comprises selecting the protective layer as aSi₃N₄ barrier layer.
 3. The method according to claim 2, which furthercomprises depositing the Si₃N₄ barrier layer with an LPCVD processor. 4.The method according to claim 2, which further comprises carrying outthe step of applying the protective layer by: depositing a SiO₂ bufferlayer; and depositing a Si₃N₄ barrier layer on the SiO₂ buffer layer. 5.The method according to claim 1, which further comprises selecting theprotective layer as a SiO₂ barrier layer.
 6. The method according toclaim 1, which further comprises constructing the protective layer as athree-layer barrier layer structure having a polysilicon sublayerembedded in two SiO₂ sublayers.
 7. The method according to claim 1,which further comprises constructing the protective layer as amultilayer barrier layer structure having alternating SiO₂ andpolysilicon sublayers.
 8. The method according to claim 1, which furthercomprises providing the protective layer with a thickness of greaterthan 30 nm.
 9. The method according to claim 1, which further comprisesproviding the protective layer with a thickness of greater than 100 nm.10. The method according to claim 1, which further comprises doping theprotective layer with a substance acting as a trapping center for the atleast one substance to be protected against.
 11. The method according toclaim 1, which further comprises doping the protective layer withphosphorus acting as a trapping center for the at least one substance tobe protected against.
 12. The method according to claim 1, which furthercomprises carrying out the step of applying the protective layer with alayer deposition process, and cleaning the protective layer for removingadsorbed substances after the layer deposition process.
 13. The methodaccording to claim 1, which further comprises damaging the back of theSi-semiconductor wafer in an area close to a surface, before applyingthe protective layer.